DFT :

JD for req1:  Find the JD for the Current DFT req :

Team Lead : 10 +yrs

Notice : immediate to 45 days 

Positions :  5

Should have worked hands-on extensively on full chip DFT design,

• Implementation, vector generation/verification, JTAG, boundary scan and simulation.

• Experience with Scan, Compression, ATPG and simulations with Mentor/Synopsys/Cadence tools. Logic BIST knowledge is a plus.

• Should have participated in successful tapeouts ofSoC/ASIC chips at 40nm or below and achieved test targets.

• Descent understanding of front-end SoC/ASIC design and implementation including Synthesis and STA.

• Develop/automate flows and scripts in Perl/Tcl to enhance the DFT methodologies & process

• Excellent problem solving and debugging skills. Proactive in nature

• Leading junior teams, Mentoring/Training and Project leadership.

• Excellent Customer interaction, Communication and Team work skills

Qualification: BE/B.Tech in ECE /M.Tech in VLSI .

JD for req2:  Find the JD for the Current DFT req :

Team Lead : 5+ yrs

Positions :  20

Notice : immediate to 45 days 

Sr.DFT Engineer 5+ yrs

Has worked on scan-stitching; and has good knowledge of scan-stitching related concepts..

- Has worked on MBISTBISR implementation and is confident with the Tessent flow of mbist-insertion..

- Has worked on ATPG; and is well conversed with the files required to run ATPG.. Knowledge experience with Tessent ATPG (mentor) is a plus

- Has worked on Spyglass-Lint.

- Knowledge on automation scripts is a plus..

- Knows the basics of JTAG & IJTAG.

- Support Spyglass debug and coverage co-relation..

- Support scan-stitching runs.. Debug DRC other scan-related issues

- Support ATPG.. debug ATPG issues.. debug coverage holes..

- Support MBISTBISR insertion.. debug insertion issues verification issues..

- Support gate-level simulations.

Qualification: BE/B.Tech in ECE /M.Tech in VLSI