• Working experience in System Verilog and OVM/UVM methodologies. (UVC creation, integration, SV coverage, SV assertions, SV constraints, UVM sequences etc)
• Should have IP/Sub-System level verification experience.
  • Develop verification plan, Build complex test-bench environments and identifying corner case scenarios, exposing Arch/corner case bugs and closing coverage
• Experience with coverage driven verification methodologies.
• Experience with High Speed Interfaces- USB, DP/eDP, PCIE, DSI, CSI,
• Knowledge in AMBA bus protocols  APB, AHB & AXI
• Experience with creating & working with Scalable and Reusable test-bench.
• Must have excellent knowledge of ASIC Verification Flow
• Excellent debug  and problem solving skills ( Should be able to reach to root-cause issues)
• Familiarity with scripting languages likes Perl, Python
• Bug tracking – JIRA/CQ
• Experience on any revision tracking tool - Perforce, SVN, CVS
• Team player, can-do attitude is desirable
• Good communication skills.

Role & Responsibilities

• Understanding the Domain, Architecture, Specifications and Design. 
• Contribute in developing verification strategy and verification environment architecture.
• Creation of Verification/Test plan.
• Creation of TB and TB components  - BFM, Drivers, Checker,  Monitors, Coverage Grids, Score-boards and reference models.
• Creation of reusable test cases and sequence  library using directed random stimulus
• Setting up of compile and elaboration flow, regression engine, test-lists etc. .
• Verification of features/sub-features of the design and debug of failures. 
• Running/Managing Regressions  and clean-up of regression failures.
• Functional and code coverage closure
• Supporting the SOC team and resolving issues/ queries related to the IP.
• Re-usability/Scalability of the test-bench
• Working with and helping other team members